Advertisement
14.8.
Control Registers ________________________________________________ 14-15
15.
Quad Synchronous Serial Interface (QSPI) ___________________________ 15-1
15.1.
Overview _______________________________________________________ 15-1
15.2.
Input/Output Pins and External Connections __________________________ 15-2
15.2.1.
List of Input/Output Pins ________________________________________________ 15-2
15.2.2.
External Connections ___________________________________________________ 15-2
15.2.3.
Pin Functions in Master Mode and Slave Mode ______________________________ 15-6
15.2.4.
Input Pin Pull-Up/Pull-Down Function _____________________________________ 15-6
15.3.
Clock Settings ___________________________________________________ 15-7
15.3.1.
QSPI Operating Clock ___________________________________________________ 15-7
15.3.2.
Clock Supply During Debugging ___________________________________________ 15-7
QSPI Clock (QSPICLK n ) Phase and Polarity ___________________________________ 15-8
15.3.3.
15.4.
Data Format ____________________________________________________ 15-8
15.5.
Operations _____________________________________________________ 15-10
15.5.1.
Register Access Mode _________________________________________________ 15-10
15.5.2.
Memory Mapped Access Mode _________________________________________ 15-10
15.5.3.
Initialization __________________________________________________________ 15-12
15.5.4.
Data Transmission in Master Mode _______________________________________ 15-13
15.5.5.
Data Reception in Register Access Master Mode ___________________________ 15-15
15.5.6.
Data Reception in Memory Mapped Access Mode __________________________ 15-18
15.5.7.
Terminating Memory Mapped Access Operations ___________________________ 15-27
15.5.8.
Terminating Data Transfer in Master Mode ________________________________ 15-27
15.5.9.
Data Transfer in Slave Mode ____________________________________________ 15-28
15.5.10.
Terminating Data Transfer in Slave Mode ________________________________ 15-29
15.6.
Interrupts _____________________________________________________ 15-30
15.7.
DMA Transfer Requests ___________________________________________ 15-32
15.8.
Control Registers ________________________________________________ 15-33
2
16.
I
C (I2C) ______________________________________________________ 16-1
16.1.
Overview _______________________________________________________ 16-1
16.2.
Input/Output Pins and External Connections __________________________ 16-2
16.2.1.
List of Input/Output Pins ________________________________________________ 16-2
16.2.2.
External Connections ___________________________________________________ 16-2
16.3.
Clock Settings ___________________________________________________ 16-3
16.3.1.
I2C Operating Clock ____________________________________________________ 16-3
16.3.2.
Clock Supply During Debugging ___________________________________________ 16-3
16.3.3.
Baud Rate Generator ___________________________________________________ 16-4
16.4.
Operations ______________________________________________________ 16-5
16.4.1.
Initialization __________________________________________________________ 16-5
16.4.2.
Data Transmission in Master Mode ________________________________________ 16-5
16.4.3.
Data Reception in Master Mode__________________________________________ 16-8
16.4.4.
10-bit Addressing in Master Mode _______________________________________ 16-11
16.4.5.
Data Transmission in Slave Mode_________________________________________ 16-12
16.4.6.
Data Reception in Slave Mode __________________________________________ 16-14
16.4.7.
Slave Operations in 10-bit Address Mode __________________________________ 16-15
16.4.8.
Automatic Bus Clearing Operation ________________________________________ 16-16
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
