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QSPI Ch.n Interrupt Enable Register
Register name
Bit
QSPI_nINTE
15–8
7–4
3
2
1
0
Bits 15–4
Reserved
Bit 3
OEIE
Bit 2
TENDIE
Bit 1
RBFIE
Bit 0
TBEIE
These bits enable QSPI interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
QSPI_nINTE.OEIE bit:
QSPI_nINTE.TENDIE bit: End-of-transmission interrupt
QSPI_nINTE.RBFIE bit:
QSPI_nINTE.TBEIE bit:
QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register
Register name
Bit
QSPI_nTBEDMAEN
15–0
Bits 15–0
TBEDMAEN[15:0]
These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA
channel (Ch.0– Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
QSPI Ch.n Receive Buffer Full DMA Request Enable Register
Register name
Bit
QSPI_nRBFDMAEN
15–0
Bits 15–0
RBFDMAEN[15:0]
These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA
channel (Ch.0– Ch.15) when a receive buffer full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
15-38
Bit name
Initial
–
0x00
–
0x0
OEIE
0
TENDIE
0
RBFIE
0
TBEIE
0
Overrun error interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name
Initial
TBEDMAEN[15:0]
0x0000
Bit name
Initial
RBFDMAEN[15:0]
0x0000
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Reset
R/W
H0
R/W
Reset
R/W
–
R/W
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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