Epson S1C31D50 Technical Instructions page 381

CLGOSC3
0x0020
(CLG OSC3
0048
Control Register)
CLGINTF
0x0020
(CLG Interrupt
004c
Flag Register)
CLGINTE
0x0020
(CLG Interrupt
004e
Enable Register)
CLGFOUT
0x0020
(CLG FOUT
0050
Control Register)
0x0020 0080
Address Register name
CACHECTL
0x0020
(CACHE Control
0080
Register)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
15–12 –
11–10 OSC3FQ[1:0]
9 OSC3MD
8-6 –
5–4 OSC3INV[1:0]
3 OSC3STM
2–0 OSC3WT[2:0]
15–9 –
8 OSC3TERIF
7 –
6 –
5 OSC1STPIF
4 OSC3TEDIF
3 –
2 OSC3STAIF
1 OSC1STAIF
0 IOSCSTAIF
15–9 –
8 OSC3TERIE
7 –
6 –
5 OSC1STPIE
4 OSC3TEDIE
3 –
2 OSC3STAIE
1 OSC1STAIE
0 IOSCSTAIE
15–8 –
7 –
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1 –
0 FOUTEN
Cache Controller (CACHE)
Bit Bit name
15–8 –
7–2 –
1 –
0 CACHEEN
Seiko Epson Corporation
0x00 – R
0x1 H0 R/WP
0 H0 R/WP
0x0 – R
0x3 H0 R/WP
0 H0 R/WP
0x6 H0 R/WP
0x00 – R
0 H0 R/W
0 – R
0 – R
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 H0 R/W
0 – R
0 – R
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 – R
0x0 H0 R/W
0x0 H0 R/W
0 – R
0 H0 R/W
Initial Reset R/W
0x00 – R
0x00 – R
0 – R
0 H0 R/W
–
–
Cleared by writing 1.
–
Cleared by writing 1.
–
Cleared by writing 1.
–
–
Remarks
–
B-3