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REMC3 Data Bit Counter Control Register
Register name
Bit
REMC3DBCTL
15–10
9
8
7–5
4
3
2
1
0
Bits 15–10
Reserved
Bit 9
PRESET
This bit resets the internal counters (16-bit counter for data signal generation and 8-bit
counter for carrier generation).
1 (W):
0 (W):
1 (R):
0 (R):
Before the counter can be reset using this bit, the REMC3DBCTL.MODEN bit must be set to
1.
This bit is cleared to 0 after the counter reset operation has finished or when 1 is written to
the REMC3DBCTL.REMCRST bit.
Bit 8
PRUN
This bit starts/stops counting by the internal counters (16-bit counter for data signal
generation and 8-bit counter for carrier generation).
1 (W):
0 (W):
1 (R):
0 (R):
Before the counter can start counting by this bit, the REMC3DBCTL.MODEN bit must be set
to 1. While the counter is running, writing 0 to the REMC3DBCTL.PRUN bit stops count
operations. When the counter stops by occurrence of a compare DB in one-shot mode,
this bit is automatically cleared to 0.
Bits 7–5
Reserved
Bit 4
REMOINV
This bit inverts the REMO output signal.
1 (R/W): Inverted
0 (R/W): Non-inverted
For more information, see Figure 18.4.3.1.
Bit 3
BUFEN
This bit enables or disables the compare buffers.
1 (R/W): Enable
0 (R/W): Disable
For more information, refer to "Continuous Data Transmission and Compare Buffers."
Note:
The REMC3DBCTL.BUFEN bit must be set to 0 when setting the data signal duty and cycle
for the first time.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
PRESET
0
PRUN
0
–
0x0
REMOINV
0
BUFEN
0
TRMD
0
REMCRST
0
MODEN
0
Reset
Ineffective
Resetting in progress
Resetting finished or normal operation
Start counting
Stop counting
Counting
Idle
Seiko Epson Corporation
Reset
R/W
–
R
H0/S0
R/W
Cleared by writing 1 to the
H0/S0
R/W
REMC3DBCTL.REMCRST bit.
–
R
H0
R/W
H0
R/W
H0
R/W
H0
W
H0
R/W
Remarks
–
–
18-9
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