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7.3.3.
Clock Supply During Debugging ____________________________________________ 7-3
7.4.
Operations _________________________________________________________ 7-4
7.4.1.
Initialization ____________________________________________________________ 7-4
7.4.2.
Port Input/Output Control ________________________________________________ 7-6
7.5.
Interrupts _________________________________________________________ 7-7
7.6.
Control Registers ____________________________________________________ 7-8
7.7.
Control Register and Port Function Configuration of this IC __________________ 7-14
7.7.1.
P0 Port Group _________________________________________________________ 7-14
7.7.2.
P1 Port Group _________________________________________________________ 7-15
7.7.3.
P2 Port Group _________________________________________________________ 7-16
7.7.4.
P3 Port Group _________________________________________________________ 7-17
7.7.5.
P4 Port Group _________________________________________________________ 7-18
7.7.6.
P5 Port Group _________________________________________________________ 7-19
7.7.7.
P6 Port Group _________________________________________________________ 7-20
7.7.8.
P7 Port Group _________________________________________________________ 7-21
7.7.9.
P8 Port Group _________________________________________________________ 7-22
7.7.10.
P9 Port Group _________________________________________________________ 7-23
7.7.11.
PA Port Group _________________________________________________________ 7-24
7.7.12.
PD Port Group _________________________________________________________ 7-25
7.7.13.
Common Registers between Port Groups ___________________________________ 7-26
8.
Universal Port Multiplexer (UPMUX) __________________________________ 8-1
8.1.
Overview __________________________________________________________ 8-1
8.2.
Peripheral Circuit I/O Function Assignment _______________________________ 8-1
8.3.
Control Registers ____________________________________________________ 8-2
9.
Watchdog Timer (WDT2) ____________________________________________ 9-1
9.1.
Overview __________________________________________________________ 9-1
9.2.
Clock Settings ______________________________________________________ 9-1
9.2.1.
WDT2 Operating Clock ___________________________________________________ 9-1
9.2.2.
Clock Supply in DEBUG Mode _____________________________________________ 9-1
9.3.
Operations_________________________________________________________ 9-2
9.3.1.
WDT2 Control __________________________________________________________ 9-2
9.3.2.
Operations in HALT and SLEEP Modes _______________________________________ 9-3
9.4.
Control Registers ____________________________________________________ 9-4
10.
Real-Time Clock (RTCA) __________________________________________ 10-1
10.1.
Overview _______________________________________________________ 10-1
10.2.
Output Pin and External Connection _________________________________ 10-1
10.2.1.
Output Pin ____________________________________________________________ 10-1
10.3.
Clock Settings ___________________________________________________ 10-2
10.3.1.
RTCA Operating Clock __________________________________________________ 10-2
10.3.2.
Theoretical Regulation Function __________________________________________ 10-2
10.4.
Operations ______________________________________________________ 10-4
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
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