Advertisement
14. Synchronous Serial Interface (SPIA)
14.1. Overview
SPIA is a synchronous serial interface. The features of SPIA are listed below.
•
Supports both master and slave modes.
•
Data length: 2 to 16 bits programmable
•
Either MSB first or LSB first can be selected for the data format.
•
Clock phase and polarity are configurable.
•
Supports full-duplex communications.
•
Includes separated transmit data buffer and receive data buffer registers.
•
Can generate receive buffer full, transmit buffer empty, end of transmission, and overrun
interrupts.
•
Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs.
•
Master mode allows use of a 16-bit timer to set baud rate.
•
Slave mode is capable of being operated with the external input clock SPICLKn only.
•
Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt.
Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration.
Item
Number of channels
Internal clock input
16-bit timer
CLK_T16_m
Clock
generator
Timer
Underflow
CPU core
DMA
controller
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 14.1.1 SPIA Channel Configuration of S1C31D50
Ch.0 ← 16-bit timer Ch.1 Ch.1 ← 16-bit timer Ch.6
NOCLKDIV
CLK_SPIA
n
1/2
Clock/shift
register
control circuit
MODEN
SFTRST
LSBFST
CPHA
CPOL
Pull
up/down
-
PUEN
control
circuit
Interrupt
TENDIE
control circuit
RBFIE
TBEIE
DMA request
RBFDMAEN
control circuit
TBEDMAEN
Figure 14.1.1 SPIA Configuration
Seiko Epson Corporation
S1C31D50
3 channels (Ch.0 , Ch.1 and Ch.2)
Ch.2 ← 16-bit timer Ch.5
Shift register
Transmit data
buffer
TXD[15:0]
Receive data buffer
RXD[15:0]
(Used only in slave mode)
TENDIF
RBFIF
TBEIF
V
DD
SDIn
SDOn
V
DD
SPICLKn
V
DD
V
SS
#SPISSn
14-1
Advertisement
