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QSPI Ch.n FIFO Data Ready DMA Request Enable Register
Register name
Bit
QSPI_nFRLDMAEN
15–8
Bits 15–0
FRLDMAEN[15:0]
These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA
channel (Ch.0– Ch.15) when data is prefetched into the FIFO (FIFO data ready).
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
QSPI Ch.n Memory Mapped Access Configuration Register 1
Register name
Bit
QSPI_nMMACFG1
15–8
7–4
3–0
Bits 15–4
Reserved
Bits 3–0
TCSH[3:0]
When non-sequential reading from a Flash memory address, which is not continuous to
the previous read address, occurs in memory mapped access mode, the #QSPISSn signal is
reasserted after negated once. Then the new address is sent to the Flash memory before
reading data.
The QSPI_nMMACFG1.TCSH[3:0] bits specify the period to negate the #QSPISSn signal at
this time in a number of clocks.
Table 15.8.4 #QSPISSn Inactive Period between Non-Sequential Readings
QSPI_nMMACFG1.TCSH[3:0] bits
Note:
These bits specify a number of system clocks.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
FRLDMAEN[15:0]
0x0000
Bit name
Initial
–
0x00
–
0x0
TCSH[3:0]
0x0
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
–
R
–
R
H0
R/W
#QSPISSn Inactive Period
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
1 clock
Remarks
–
Remarks
–
15-39
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