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The time from counter = 0x0000 or MAX value to occurrence of a compare interrupt (compare
period) and the time to occurrence of a counter MAX or counter zero interrupt (count cycle) can be
calculated as follows:
During counting up
Compare period
During counting down
Compare period =
Where
CC:
T16B_nCCRm register setting value (0 to 65,535)
MAX:
T16B_nMC register setting value (0 to 65,535)
f
: Count clock frequency [Hz]
CLK_T16B
The comparator MATCH signal and counter MAX/ZERO signals are also used to generate a timer
output wave- form (TOUT). Refer to "TOUT Output Control" for more information.
Compare buffer
The comparator loads the comparison value, which has been written to the T16B_nCCRm register,
to the compare buffer before comparing it with the counter value. For example, when generating a
PWM wave- form, the waveform with the desired duty ratio may not be generated if the
comparison value is altered asynchronous to the count operation. To avoid this problem, the timing
to load the comparison value to the compare buffer can be configured using the
T16B_nCCCTLm.CBUFMD[2:0] bits for synchronization with the count operation.
(1) Repeat up count mode
T16B_nCCCTLm.CBUFMD[2:0] bits = 0x0
1.1)
Data (W) → CC[15:0]
Data (W) → MC[15:0]
MODEN = 1
PRESET = 1
RUN = 1
0xffff
Compare period
Counter
0x0000
17-10
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=
[s]
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(���� + 1)
[s]
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Data (W) → CC[15:0]
Count cycle
CNTMAXIF = 1
CNTMAXIF = 1
CMPCAPmIF = 1
CMPCAPmIF = 1
Seiko Epson Corporation
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Count cycle
=
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Count cycle =
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Software operation
Hardware operation
Data (W) → CC[15:0]
CNTMAXIF = 1
CMPCAPmIF = 1
[s]
(����. 17.1)
[s]
(����. 17.2)
MAX value
(T16B_nMC register)
Compare buffer
value
Time
CMPCAPmIF = 1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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