Advertisement
Data transmission
Write 1 to the I2C_nCTL.TXSTART bit
Wait for an interrupt request
(I2C_nINTF.TBEIF = 1)
Write slave address and WRITE (0) to
the I2C_nTXD register
Wait for an interrupt request
(I2C_nINTF.TBEIF = 1 or I2C_nINTF.NACKIF = 1)
I2C_nINTF.NACKIF = 1 ?
Yes
Write 1 to the I2C_nCTL.TXSTOP bit
Wait for an interrupt request
(I2C_nINTF.STOPIF = 1)
Figure 16.4.2.2 Master Mode Data Transmission Flowchart
Data transmission using DMA
By setting the I2C_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and transmit data is transferred from the specified
memory to the I2C_ nTXD register via DMA Ch.x when the I2C_nINTF.TBEIF bit is set to 1 (transmit
buffer empty).
This automates the data sending procedure from Steps 5, 6, and 8 described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance so that transmit data
will be transferred to the I2C_ nTXD register. For more information on DMA, refer to the "DMA
Controller" chapter.
Table 16.4.2.1 DMA Data Structure Configuration Example (for Data Transmission)
End pointer
Control data
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
No
Last data sent?
Yes
Retry?
No
End
Item
Transfer source
Memory address in which the last transmit data is stored
Transfer destination
I2C_nTXD register address
dst_inc
0x3 (no increment)
dst_size
0x0 (byte)
src_inc
0x0 (+1)
src_size
0x0 (byte)
R_power
0x0 (arbitrated for every transfer)
n_minus_1
Number of transfer data
cycle_ctrl
0x1 (basic transfer)
Seiko Epson Corporation
No
Yes
Write data to the I2C_nTXD register
Setting example
16-7
Advertisement
