Epson S1C31D50 Technical Instructions page 36

CLG
OSC1
X'tal1
OSC2
OSC3
X'tal3/
OSC4
Ceramic3
EXOSC
FOUT
FOUTDIV[2:0]
2.3.2. Input/Output Pins
Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC1
Ａ
OSC2 A
OSC3 A
OSC4 A
EXOSC I
FOUT O
* Indicates the status when the pin is configured for CLG.
If the port is shared with the CLG input/output function and other functions, the CLG function must
be assigned to the port. For more information, refer to the "I/O Ports" chapter.
2-8
IOSCEN
IOSC
IOSCCLK
oscillator
Divider
circuit
OSC1EN
OSC1
OSC1CLK
oscillator
Divider
circuit
OSC3EN
OSC3
OSC3CLK
oscillator Divider
circuit
EXOSCEN
EXOSC
EXOSCCLK
clock input
circuit
FOUTEN
FOUT
output
circuit
Figure 2.3.1.1 CLG Configuration
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC1 oscillator circuit input
– OSC1 oscillator circuit output
– OSC3 oscillator circuit input
– OSC3 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
Seiko Epson Corporation
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
SYSCLK
Clock
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
Function
S1C31D50 TECHNICAL MANUAL
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
(Rev. 1.00)