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11.3. Clock Settings
11.3.1. SVD3 Operating Clock
When using SVD3, the SVD3 operating clock CLK_SVD3 must be supplied to SVD3 from the clock
generator. The CLK_SVD3 supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the
"Power Supply, Reset, and Clocks" chapter).
3. Set the following SVD3CLK register bits:
SVD3CLK.CLKSRC[1:0] bits (Clock source selection)
-
SVD3CLK.CLKDIV[2:0] bits (Clock division ratio selection = Clock frequency setting)
-
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
The CLK_SVD3 frequency should be set to around 32 kHz.
11.3.2. Clock Supply in SLEEP Mode
When using SVD3 during SLEEP mode, the SVD3 operating clock CLK_SVD3 must be configured so that
it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is
deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before
entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3
operation resumes.
11.3.3. Clock Supply in DEBUG Mode
The CLK_SVD3 supply during DEBUG mode should be controlled using the SVD3CLK.DBRUN bit.
The CLK_SVD3 supply to SVD3 is suspended when the CPU enters DEBUG mode if the SVD3CLK.DBRUN
bit= 0. After the CPU returns to normal mode, the CLK_SVD3 supply resumes. Although SVD3 stops
operating when the CLK_SVD3 supply is suspended, the registers retain the status before DEBUG mode
was entered.
If the SVD3CLK.DBRUN bit = 1, the CLK_SVD3 supply is not suspended and SVD3 will keep operating in
DE- BUG mode.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
11-3
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