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23.13. 12-bit A/D Converter (ADC12A) Characteristics
Unless otherwise specified: V
(7cycles)
Item
VREFAn voltage range
V
A/D conversion clock
f
frequency
Sampling rate
f
*1
Integral nonlinearity
*2
INL
Differential nonlinearity
DNL
Zero-scale error
ZSE
Full-scale error
FSE
Analog input resistance
R
Analog input capacitance
C
A/D converter circuit
I
current
*1 The Max. value is the value when the A/D conversion clock frequency f
*2 Integral nonlinearity is measured at the end point line.
*3 The error will be increased according to the potential difference between V
A/D converter current consumption-power supply voltage characteristic
V
= V
, ADIN = V
/2, f
= 100 ksps, Ta = 25 °C, Typ. value
DD
REFA
REFA
SMP
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
= 2.5 to 5.5 V, VREFAn = 1.8 to 5.5 V, V
DD
Symbol
Condition
REFA
CLK_ADC12A
SMP
VDD = VREFAn *3
VDD = VREFAn *3
VDD = VREFAn *3
VDD = VREFAn *3
ADIN
ADIN
ADC12A_nCFG.VRANGE[1:0] bits = 0x3,
ADC
V
= V
, ADIN = V
DD
REFA
Ta = 25 °C
ADC12A_nCFG.VRANGE[1:0] bits = 0x2,
V
= V
, ADIN = V
DD
REFA
Ta = 25 °C
ADC12A_nCFG.VRANGE[1:0] bits = 0x1,
V
= V
, ADIN = V
DD
REFA
= 25 °C
Seiko Epson Corporation
= 0 V, Ta = -40 to 85 °C, ADC12A_nTRG.SMPCLK[2:0] bits = 0x3
SS
V
DD
3.6 V
/2, f
= 100 ksps,
REFA
SMP
4.8 V
/2, f
= 100 ksps,
REFA
SMP
5.5 V
/2, f
= 100 ksps, Ta
REFA
SMP
= 2,000 kHz.
CLK_ADC12A
and VREFAn.
DD
Min.
Typ.
Max.
Unit
1.8
–
V
V
DD
16
–
2,200
kHz
–
–
100
ksps
–
–
±3
LSB
–
–
±3
LSB
–
–
±5
LSB
–
–
±5
LSB
–
–
4
kW
–
–
30
pF
–
400
700
µA
–
230
470
µA
–
210
390
µA
23-17
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