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RTCA Second/1Hz Register
Register name
Bit
RTCASEC
15
14–12
11–8
7
6
5
4
3
2
1
0
Bit 15
Reserved
Bits 14–12
RTCSH[2:0]
Bits 11–8
RTCSL[3:0]
The RTCASEC.RTCSH[2:0] bits and the RTCASEC.RTCSL[3:0] bits are used to set and read
the 10-second digit and the 1-second digit of the second counter, respectively. The
setting/read values are a BCD code within the range from 0 to 59.
Note:
Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL.
RTCBSY bit = 1.
Bit 7
RTC1HZ
Bit 6
RTC2HZ
Bit 5
RTC4HZ
Bit 4
RTC8HZ
Bit 3
RTC16HZ
Bit 2
RTC32HZ
Bit 1
RTC64HZ
Bit 0
RTC128HZ
1 Hz counter data can be read from these bits.
The following shows the correspondence between the bit and frequency:
RTCASEC.RTC1HZ bit:
RTCASEC.RTC2HZ bit:
RTCASEC.RTC4HZ bit:
RTCASEC.RTC8HZ bit:
RTCASEC.RTC16HZ bit:
RTCASEC.RTC32HZ bit:
RTCASEC.RTC64HZ bit:
RTCASEC.RTC128HZ bit: 128 Hz
Note:
The counter value may not be read correctly while the 1 Hz counter is running. These bits
must be read twice and assume the counter value was read successfully if the two read re-
sults are the same.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0
RTCSH[2:0]
0x0
RTCSL[3:0]
0x0
RTC1HZ
0
RTC2HZ
0
RTC4HZ
0
RTC8HZ
0
RTC16HZ
0
RTC32HZ
0
RTC64HZ
0
RTC128HZ
0
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
H0
R
Cleared by setting the
H0
R
RTCACTLL.RTCRST bit to 1.
H0
R
H0
R
H0
R
H0
R
H0
R
H0
R
Remarks
–
10-13
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