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SPIA Ch.n Interrupt Flag Register
Register name
Bit
SPIA_nINTF
15–8
7
6–4
3
2
1
0
Bits 15–8
Reserved
Bit 7
BSY
This bit indicates the SPIA operating status.
1 (R): Transmit/receive busy (master mode), #SPISSn = Low level (slave mode)
0 (R): Idle
Bits 6–4
Reserved
Bit 3
OEIF
Bit 2
TENDIF
Bit 1
RBFIF
Bit 0
TBEIF
These bits indicate the SPIA interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag (OEIF, TENDIF)
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
SPIA_nINTF.OEIF bit:
SPIA_nINTF.TENDIF bit:
SPIA_nINTF.RBFIF bit:
SPIA_nINTF.TBEIF bit:
14-18
Bit name
Initial
Reset
–
0x00
BSY
0
–
0x0
OEIF
0
H0/S0
TENDIF
0
H0/S0
RBFIF
0
H0/S0
TBEIF
1
H0/S0
Overrun error interrupt
End-of-transmission interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Seiko Epson Corporation
R/W
–
R
–
H0
R
–
R
R/W
Cleared by writing 1.
R/W
R
Cleared by reading the SPIA_nRXD
register.
R
Cleared by writing to the SPIA_nTXD
register.
S1C31D50 TECHNICAL MANUAL
Remarks
(Rev. 1.00)
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