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7. I/O Ports (PPORT)
7.1. Overview
PPORT controls the I/O ports. The main features are outlined below.
•
Allows port-by-port function configurations.
Each port can be configured with or without a pull-up or pull-down resistor.
-
Each port can be configured with or without a chattering filter.
-
Allows selection of the function (general-purpose I/O port (GPIO) function, up to four peripheral
-
I/O functions) to be assigned to each port.
•
Ports, except for those shared with debug pins, are initially placed into Hi-Z state. (No current passes
through the pin during this Hi-Z state.)
Note: 'x', which is used in the port names Pxy, register names, and bit names, refers to a port group (x=
0, 1, 2, ··· , d) and 'y' refers to a port number (y = 0, 1, 2, ··· , 7).
Figure 7.1.1 shows the configuration of PPORT.
Item
Port groups included
Ports with general-purpose I/O function (GPIO)
Ports with interrupt function
Ports for debug function
Peripheral I/O function 0 I/O control
Peripheral I/O function 1 I/O control
Peripheral I/O function 2 I/O control
Peripheral I/O function 3 I/O control
Clock
generator
System reset
controller
CPU core
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 7.1.1 Port Configuration of S1C31D50
PPORT
Pxy
PxSELy
PxyMUX[1:0]
PxOUTy
PxOENy
PxIENy
PxPDPUy
PxRENy
PxCHATENy
CLKSRC[1:0]
PxINy
CLKDIV[3:0]
DBRUN
PxEDGEy
Key-entry
Key-entry
reset signal
PxEDGEy
reset control
PxINT
circuit
PxIFy
KRSTCFG[1:0]
PxIEy
Figure 7.1.1 PPORT Configuration
Seiko Epson Corporation
S1C31D50
P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0], P7[7:0]
P8[7:0],P9[5:0],PA[6:0],PD[5:0]
P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0].P7[7:0]
P8[7:0],P9[5:0],PA[6:0]
PD[1:0]
GPIO/
peripheral I/O
GPIO function
function
switching
General-purpose
I/O control
circuit
Chattering
filter
Interrupt
control circuit
Exist only in the ports that supports the interrupt function.
I/O cell
control signal
Output signal
I/O
Pxy
cell
Input signal
7-1
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