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14.2.3. Pin Functions in Master Mode and Slave Mode
The pin functions are changed according to the master or slave mode selection. The differences in pin
functions be- tween the modes are shown in Table 14.2.3.1.
Pin
SDIn
SDOn
Always placed into output state.
SPICLKn Outputs the SPI clock to external devices.
Output clock polarity and phase can be configured
if necessary.
#SPISSn Not used.
This input function is not required to be assigned to
the port. To output the slave select signal in master
mode, use a general-purpose I/O port function.
14.2.4. Input Pin Pull-Up/Pull-Down Function
The SPIA input pins (SDIn in master mode or SDIn, SPICLKn, and #SPISSn pins in slave mode) have a
pull-up or pull-down function as shown in Table 14.2.4.1. This function is enabled by setting the
SPIA_nMOD.PUEN bit to 1.
Pin
SDIn
SPICLKn
#SPISSn
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 14.2.3.1 Pin Function Differences between Modes
Function in master mode
Always placed into input state.
Table 14.2.4.1 Pull-Up or Pull-Down of Input Pins
Master mode
Pull-up
–
–
Seiko Epson Corporation
Function in slave mode
This pin is placed into output state while a low level
is applied to the #SPISSn pin or placed into Hi-Z
state while a high level is applied to the #SPISSn
pin.
Inputs an external SPI clock.
Clock polarity and phase can be designated accord-
ing to the input clock.
Applying a low level to the #SPISSn pin enables
SPIA to transmit/receive data. While a high level is
applied to this pin, SPIA is not selected as a slave
device. Data input to the SDIn pin and the clock
input to the SPICLKn pin are ignored. When a high
level is applied, the transmit/receive bit count is
cleared to 0 and the already received bits are dis-
carded.
Slave mode
Pull-up
SPIA_nMOD.CPOL bit = 1: Pull-up
SPIA_nMOD.CPOL bit = 0: Pull-down
Pull-up
14-3
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