Advertisement
DMA transfer procedure
1. Configure the data structure table for scatter-gather transfer.
Set the cycle_ctrl for the last task to 0x1 and those for other tasks to 0x7.
2. Start data transfer by following the procedure shown in Section 6.2.1, "Initialization." In Step 2 of
the initialization procedure, configure the primary data structure with the control data shown
below.
Transfer source end pointer = Data structure table end address
Transfer destination end pointer = Alternate data structure end address dst_inc = 0x2
dst_size = 0x2
src_inc = 0x2
src_size = 0x2
R_power = 0x2
n_minus_1 = Number of tasks × 4 – 1
cycle_ctrl = 0x6
3. Issue a DMA transfer request in each task using a peripheral circuit or via software.
4. The DMA transfer is completed when a DMA transfer completion interrupt occurs.
6.6. DMA Transfer Cycle
A DMA transfer requires several clock cycles to execute. Figure 6.6.1 shows a detailed DAM transfer
cycle. Note that the number of clock cycles for a DMA transfer may be increased due to a conflict
with an access from the CPU or the Flash bus access cycle setting.
SYSCLK
Transfer cycle
6.7. Interrupts
The DMAC has a function to generate the interrupts shown in Table 6.7.1.
Interrupt
DMA transfer
completion
DMA transfer error
The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request
is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the
interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
6-12
IDLE
rc
rsp
DMA transfer request
Figure 6.6.1 DMA Transfer Cycle
Table 6.7.1 DMAC Interrupt Function
Interrupt flag
DMACENDIF.ENDIFn
When DMA transfers for a set number of
successive transfers have completed
DMACERRIF.ERRIF
When an AHB bus error has occurred
Seiko Epson Corporation
rdp
RD WD
wc IDLE
rc:
Read control data
rsp: Read transfer source end pointer
rdp: Read transfer destination end pointer
RD: Read data from transfer source
WD: Write data to transfer destination
wc: Write control data
Set condition
rc
rsp
Clear condition
Writing 1
Writing 1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
