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Epson S1C31D50 Technical Instructions page 123

Cmos 32-bit single chip microcontroller
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10.3. Clock Settings
10.3.1. RTCA Operating Clock
RTCA uses CLK_RTCA, which is generated by the clock generator from OSC1 as the clock source, as its
operating clock. RTCA is operable when OSC1 is enabled.
To continue the RTCA operation during SLEEP mode with OSC1 being activated, the
CLGOSC.OSC1SLPC bit must be set to 0.
10.3.2. Theoretical Regulation Function
The time-of-day clock loses accuracy if the OSC1 frequency f
kHz. To correct this error without changing any external part, RTCA provides a theoretical regulation
function. Follow the procedure below to perform theoretical regulation.
1.
Measure the frequency tolerance "m [ppm]" of f
2.
Determine the theoretical regulation execution cycle time "n seconds."
3.
Determine the value to be written to the RTCACTLH.RTCTRM[6:0] bits from the results in Steps 1
and 2.
4.
Write the value determined in Step 3 to the RTCACTLH.RTCTRM[6:0] bits periodically in n-second
cycles using an RTCA alarm or second interrupt.
5.
Monitor the RTC1S signal to check that every n-second cycle has no error included.
The correction value for theoretical regulation can be specified within the range from -64 to +63 and it
should be written to the RTCACTLH.RTCTRM[6:0] bits as a two's-complement number. Use Eq. 10.1 to
calculate the correction value.
��
������������[6: 0] =
6
10
Where
n: Theoretical regulation execution cycle time [second] (time interval to write the correct
value to the RTCACTLH.RTCTRM[6:0] bits periodically via software)
m: OSC1 frequency tolerance [ppm]
Figure 10.3.2.1 shows the RTC1S signal waveform.
RTC1S
RTCACTLH.RTCTRMBSY
10-2
× 256 × n (However, RTCTRM[6: 0] is an integer after rounding off to − 64 to + 63. ) (Eq. 10.1)
Theoretical regulation execution cycle time n [s]
32,768/fOSC1 [s]
Writing to the RTCACTLH.RTCTRM[6:0] bits
*∆ T = correction time set in the RTCACTLH.RTCTRM[6:0] bits
Figure 10.3.2.1 RTC1S Signal Waveform
Seiko Epson Corporation
has a frequency tolerance from 32.768
OSC1
.
OSC1
32,768/fOSC1 ± ∆T [s]
Theoretical regulation
completion interrupt
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)

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