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Synchronous capture mode/asynchronous capture mode
The capture circuit can operate in two operating modes: synchronous capture mode and
asynchronous capture mode.
Synchronous capture mode is provided to avoid the possibility of invalid data reading by capturing
counter data simultaneously with the counter being counted up/down. Set the T16B_nCCCTLm.SCS
bit to 1 to set the capture circuit to synchronous capture mode. This mode captures counter data
by synchronizing the capture signal with the counter clock.
On the other hand, asynchronous capture mode can capture counter data by detecting a trigger
pulse even if the pulse is shorter than the counter clock cycle that becomes invalid in synchronous
capture mode. Set the T16B_nCCCTLm.SCS bit to 0 to set the capture circuit to asynchronous capture
mode.
Synchronous capture mode
(1)
Count clock
T16B_nTC.TC[15:0]
Capture trigger signal
T16B_nCCRm.CC[15:0]
Capturing operation
Asynchronous capture mode
(2)
Count clock
T16B_nTC.TC[15:0]
Capture trigger signal
T16B_nCCRm.CC[15:0]
Capturing operation
Figure 17.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode
Capture data transfer using DMA
By setting the T16B_nCCmDMAEN.CCmDMAENx bit to 1 (DMA transfer request enabled) in
capture mode, a DMA transfer request is sent to the DMA controller and the T16B_nCCRm register
value is transferred to the specified memory via DMA Ch.x when the T16B_nINTF.CMPCAPmIF bit is
set to 1 (when data has been captured).
This automates reading and saving of capture data.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information
on DMA, refer to the "DMA Controller" chapter.
Table 17.4.3.2 DMA Data Structure Configuration Example (Capture Data Transfer)
End pointer
Transfer source
Transfer destination Memory address to which the last capture data is stored
Control data dst_inc
dst_size
src_inc
src_size
R_power
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
0
1
2
3
1
0
1
2
3
1
Item
T16B_nCCRm register address
0x1 (+2)
0x1 (haflword)
0x3 (no increment)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Seiko Epson Corporation
(When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3)
4
5
6
7
8
9
(When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3)
4
5
6
7
8
9
5
Setting example
10
11
12
13
14
5
10
11
12
13
14
10
11
17-17
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