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9. Watchdog Timer (WDT2)
9.1. Overview
WDT2 restarts the system if a problem occurs, such as when the program cannot be executed normally.
The features of WDT2 are listed below.
•
Includes a 10-bit up counter to count NMI/reset generation cycle.
•
A counter clock source and clock division ratio are selectable.
•
Can generate a reset or NMI in a cycle given via software.
•
Can generate a reset at the next NMI generation cycle after an NMI is generated.
Figure 9.1.1 shows the configuration of WDT2.
WDT2
Clock
generator
9.2. Clock Settings
9.2.1. WDT2 Operating Clock
When using WDT2, the WDT2 operating clock CLK_WDT2 must be supplied to WDT2 from the clock
generator. The CLK_WDT2 supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the
"Power Supply, Reset, and Clocks" chapter).
3. Set the following WDT2CLK register bits:
WDT2CLK.CLKSRC[1:0] bits
WDT2CLK.CLKDIV[1:0] bits
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
9.2.2. Clock Supply in DEBUG Mode
The CLK_WDT2 supply during DEBUG mode should be controlled using the WDT2CLK.DBRUN bit.
The CLK_WDT2 supply to WDT2 is suspended when the CPU enters DEBUG mode if the
WDT2CLK.DBRUN bit = 0. After the CPU returns to normal mode, the CLK_WDT2 supply resumes.
Although WDT2 stops operating when the CLK_WDT2 supply is suspended, the register retains the status
before DEBUG mode was entered.
If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in
DE- BUG mode.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Mode setting circuit
MOD[1:0]
WDTRUN[3:0]
WDTCNTRST
10-bit counter
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
Figure 9.1.1 WDT2 Configuration
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Seiko Epson Corporation
Comparator
CMP[9:0]
(Remove system protection)
NMI
STATNMI
Reset
request
9-1
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