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I2C Ch.n Receive Buffer Full DMA Request Enable Register
Register name
Bit
I2C_nRBFDMAEN
15–0
Bits 15–0
RBFDMAEN[15:0]
These bits enable the I2C to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when a receive buffer full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
RBFDMAEN[15:0]
0x0000
Seiko Epson Corporation
Reset
R/W
H0
R/W
Remarks
–
16-27
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