Advertisement
QSPI_nMOD register
CPOL bit
CPHA bit
1
0
Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read
15-24
HCLK
HSEL
HADDR
n
HTRANS
2
HSIZE
0/1
HREADY
HRDATA
1
QSPICLKn
0
QSDIOn[3:0]
Seiko Epson Corporation
n
Data cycle
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
