Epson S1C31D50 Technical Instructions page 439

DMACPASET
0x0020 (DMAC Primary-
1030 Alternate Set
Register)
DMACPACLR
0x0020 (DMAC Primary-
1034 Alternate Clear
Register)
DMACPRSET
0x0020
(DMAC Priority
1038
SetRegister)
DMACPRCLR
0x0020
(DMAC Priority
103c
Clear Register)
DMACERRIF
0x0020 (DMAC Error
104c Interrupt Flag
Register)
DMACENDIF
(DMAC Transfer
0x0020
Completion
2000
Interrupt
Flag Register)
DMACENDIESET
(DMAC Transfer
0x0020 Completion
2008 Interrupt
Enable Set
Register)
DMACENDIECLR
(DMAC Transfer
0x0020
Completion
200c
Interrupt Enable
Clear Register)
DMACERRIESET
(DMAC Error
0x0020
Interrupt
2010
Enable Set
Register)
DMACERRIECLR
(DMAC Error
0x0020
Interrupt
2014
Enable Clear
Register)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PASET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PACLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRCLR[3:0]
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIF
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIF[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIESET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIECLR[3:0]
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIESET
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIECLR
Seiko Epson Corporation
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
– – W
–
–
–
–
–
Cleared by writing 1.
Cleared by writing 1.
–
–
–
–
B-61