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3. CPU AND DEBUGGER
3.1. Overview
This IC incorporates a Cortex
3.2. CPU Core
The following shows the system configuration of the Cortex
•
Cortex
-M0+ core
®
•
32-bit single-cycle multiplier
•
Nested vectored interrupt controller (NVIC)
•
System timer (Systick)
•
Serial-wire debug port (SW-DP)
•
Micro trace buffer (MTB)
•
Number of hardware break points: 4
•
Number of watch points: 2
For detailed information on the Cortex
Manual."
3.3. Debugger
This IC includes a serial-wire debug port (SW-DP). For detailed information on the debug functions,
refer to the "Cortex
-M0+ Technical Reference Manual."
®
3.3.1. List of debugger input/output pins
Table 3.3.3.1 lists the debug pins.
Pin name
I/O
SWCLK
I
SWD
I/O
The debugger input/output pins are shared with general-purpose I/O ports and are initially set as the
debug pins. If the debugging function is not used, these pins can be switched to general-purpose I/O
port pins. For details, refer to the "I/O Ports" chapter.
3.3.2. External Connection
Figure 3.3.2.1 shows a connection example between this IC and a debugging tool when performing
debugging.
For the recommended pull-up resistor value, refer to "Recommended Operating Conditions, Debug pin
pull-up resistors R
DBG1–2
using the debug pins as general-purpose I/O port pins.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
-M0+ CPU core manufactured by U.K.-based ARM Ltd.
®
-M0+ CPU core, refer to the "Cortex
®
Table 3.3.1.1 List of Debug Pins
Initial state
I
On-chip debugger clock input pin Input a clock from a debugging tool.
I
On-chip debugger data input/output pin Used to input/output
debugging data.
S1C31 MCU
R
DBG1
SWCLK
SWD
Figure 3.3.2.1 External Connection
" in the "Electrical Characteristics" chapter. R
Seiko Epson Corporation
-M0+ CPU core embedded in this IC:
®
-M0+ Technical Reference
®
Function
V
DD
Debugging
Tool
R
DBG2
SWCLK
SWD
and R
DBG1
DBG2
are not required when
3-1
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