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DMAC Request Mask Set Register
Register name
Bit
DMACRMSET
31–0
Bits 31–0
RMSET[31:0]
These bits mask DMA transfer requests from peripheral circuits.
1 (W): Mask DMA transfer requests from peripheral circuits
0 (W): Ineffective
1 (R): DMA transfer requests from peripheral circuits have been disabled.
0 (R): DMA transfer requests from peripheral circuits have been enabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Request Mask Clear Register
Register name
Bit
DMACRMCLR
31–0
Bits 31–0
RMCLR[31:0]
These bits cancel the mask state of DMA transfer requests from peripheral circuits
1 (W): Cancel mask state of DMA transfer requests from peripheral circuits
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Enable Set Register
Register name
Bit
DMACENSET
31–0
Bits 31–0
ENSET[31:0]
These bits enable each DMAC channel.
1 (W): Enable DMAC channel
0 (W): Ineffective
1 (R): Enabled
0 (R): Disabled
These bits are cleared after the DMA transfer has completed.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Enable Clear Register
Register name
Bit
DMACENCLR
31–0
Bits 31–0
ENCLR[31:0]
These bits disable each DMAC channel.
1 (W): Disable DMAC channel (The DMACENSET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
RMSET[31:0]
0x0000
0000
Bit name
Initial
RMCLR[31:0]
–
(The DMACRMSET register is cleared to 0.)
Bit name
Initial
ENSET[31:0]
0x0000
0000
Bit name
Initial
ENCLR[31:0]
–
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
–
W
Reset
R/W
H0
R/W
Reset
R/W
–
W
Remarks
–
Remarks
–
Remarks
–
Remarks
–
6-15
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