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Bit 2
TRMD
This bit selects the operation mode of the 16-bit counter for data signal generation.
1 (R/W): One-shot mode
0 (R/W): Repeat mode
For more information, refer to "REMO Output Waveform, Data signal."
Bit 1
REMCRST
This bit issues software reset to the REMC3.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the REMC3 internal counters and interrupt flags. This bit is
automatically cleared after the reset processing has finished.
Note:
After the data signal is output in one-shot mode, set the REMC3DBCTL.REMCRST bit to 1.
Bit 0
MODEN
This bit enables the REMC3 operations.
1 (R/W): Enable REMC3 operations (The operating clock is supplied.)
0 (R/W): Disable REMC3 operations (The operating clock is stopped.)
Note:
If the REMC3DBCTL.MODEN bit is altered from 1 to 0 while sending data, the data being
sent cannot be guaranteed. When setting the REMC3DBCTL.MODEN bit to 1 again after
that, be sure to write 1 to the REMC3DBCTL.REMCRST bit as well.
REMC3 Data Bit Counter Register
Register name
Bit
REMC3DBCNT
15–0
Bits 15–0
DBCNT[15:0]
The current value of the 16-bit counter for data signal generation can be read out through
these bits.
REMC3 Data Bit Active Pulse Length Register
Register name
Bit
REMC3APLEN
15–0
Bits 15–0
APLEN[15:0]
These bits set the active pulse length of the data signal (high period when the
REMC3DBCTL.RE- MOINV bit = 0 or low period when the REMC3DBCTL.REMOINV bit = 1).
The REMO pin output is set to the active level from the 16-bit counter for data signal
generation = 0x0000 and it is inverted to the inactive level when the counter exceeds
the REMC3APLEN. APLEN[15:0] bit-setting value. The data signal duty ratio is
determined by this setting and the REMC3DBLEN.DBLEN[15:0] bit-setting. (See Figure
18.4.3.3.)
Before this register can be rewritten, the REMC3DBCTL.MODEN bit must be set to 1.
18-10
Bit name
Initial
DBCNT[15:0]
0x0000
Bit name
Initial
APLEN[15:0]
0x0000
Seiko Epson Corporation
Reset
R/W
H0/S0
R
Cleared by writing 1 to the
REMC3DBCTL.REMCRST bit.
Reset
R/W
H0
R/W
Writing enabled when
REMC3DBCTL. MODEN bit = 1.
Remarks
Remarks
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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