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Bits 2–0
OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting
CLG Interrupt Flag Register
Register name
Bit
CLGINTF
15–9
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3 Reserved
Bit 8
OSC3TERIF
Bit 5
OSC1STPIF
Bit 4
OSC3TEDIF
Bit 2
OSC3STAIF
Bit 1
OSC1STAIF
Bit 0
IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the interrupt as follows:
CLGINTF.OSC3TERIF bit: OSC3 oscillation auto-trimming error interrupt
CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt
CLGINTF.OSC3TEDIF bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note:
The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized.
2-28
CLGOSC3.OSC3WT[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name
Initial
–
0x00
OSC3TERIF
0
–
0
–
0
OSC1STPIF
0
OSC3TEDIF
0
–
0
OSC3STAIF
0
OSC1STAIF
0
IOSCSTAIF
0
Seiko Epson Corporation
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
1,024 clocks
256 clocks
64 clocks
16 clocks
4 clocks
Reset
R/W
–
R
H0
R/W
Cleared by writing 1.
–
R
–
R
H0
R/W
Cleared by writing 1.
H0
R/W
–
R
H0
R/W
Cleared by writing 1.
H0
R/W
H0
R/W
Remarks
–
–
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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