Advertisement
18.7. Control Registers
REMC3 Clock Control Register
Register name
Bit
REMC3CLK
15–9
8
7–4
3–2
1–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the REMC3 operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
Bits 7–4
CLKDIV[3:0]
These bits select the division ratio of the REMC3 operating clock.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of the REMC3.
REMC3CLK.
CLKDIV[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note:
The REMC3CLK register settings can be altered only when the REMC3DBCTL.MODEN bit =
0.
18-8
Bit name
Initial
–
0x00
DBRUN
0
CLKDIV[3:0]
0x0
–
0x0
CLKSRC[1:0]
0x0
Table 18.7.1 Clock Source and Division Ratio Settings
REMC3CLK.CLKSRC[1:0] bits
0x0
IOSC
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
–
R
H0
R/W
0x1
0x2
OSC1
OSC3
1/32,768
1/16,384
1/8,192
1/1
1/4,096
1/2,048
1/1,024
1/512
1/256
1/256
1/128
1/128
1/64
1/64
1/32
1/32
1/16
1/16
1/8
1/8
1/4
1/4
1/2
1/2
1/1
1/1
Remarks
–
0x3
EXOSC
1/1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
