Epson S1C31D50 Technical Instructions page 180

14.3.2. Clock Supply During Debugging
In master mode, the operating clock supply during debugging should be controlled using the
T16_mCLK.DBRUN bit.
The CLK_T16_m supply to SPIA Ch.n is suspended when the CPU enters debug state if the
T16_mCLK.DBRUN bit = 0. After the CPU returns to normal operation, the CLK_T16_m supply resumes.
Although SPIA Ch.n stops operating when the CLK_T16_m supply is suspended, the output pins and
registers retain the status before the de- bug state was entered. If the T16_mCLK.DBRUN bit = 1, the
CLK_T16_m supply is not suspended and SPIA Ch.n will keep operating in a debug state.
SPIA in slave mode operates with the external SPI master clock input from the SPICLKn pin regardless of
whether the CPU is placed into debug state or normal operation state.
14.3.3. SPI Clock (SPICLK n ) Phase and Polarity
The SPICLKn phase and polarity can be configured separately using the SPIA_nMOD.CPHA bit and the
SPIA_ nMOD.CPOL bit, respectively. Figure 14.3.3.1 shows the clock waveform and data input/output
timing in each setting.
SPIA_nMOD register
CPOL bit CPHA bit
1 1
1 0
0 1
0 0
x x
x x
(Master mode) SDOn
x 1 (Slave mode) SDOn
x 0 (Slave mode) SDOn
Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7)
14.4. Data Format
The SPIA data length can be selected from 2 bits to 16 bits by setting the SPIA_nMOD.CHLN[3:0] bits.
The input/ output permutation is configurable to MSB first or LSB first using the SPIA_nMOD.LSBFST
bit. Figure 14.4.1 shows a data format example when the SPIA_nMOD.CHLN[3:0] bits = 0x7, the
SPIA_nMOD.CPOL bit = 0 and the SPIA_nMOD.CPHA bit = 0.
Cycle No.
SPIA_nMOD.
SPICLKn
LSBFST bit
SDOn
0
SDIn
SDOn
1
SDIn
Figure 14.4.1 Data Format Selection Using the SPIA_nMOD.LSBFST Bit (SPIA_nMOD.CHLN[3:0] bits = 0x7,
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Cycle No. 1
SPICLKn
SPICLKn
SPICLKn
SPICLKn
MSB
SDIn
MSB
MSB
MSB
Writing data to the SPIA_nTXD register
2
1
Dw7 Dw6
Dr7 Dr6
Dw0 Dw1
Dr0 Dr1
Writing Dw[7:0] to the SPIA_nTXD register
SPIA_nMOD.CPOL bit = 0, SPIA_nMOD.CPHA bit = 0)
Seiko Epson Corporation
2 3 4
3 4 5
Dw5 Dw4 Dw3 Dw2
Dr5 Dr4 Dr3
Dw2 Dw3 Dw4 Dw5
Dr2 Dr3 Dr4
Loading Dr[7:0] to the SPIA_nRXD register
5 6 7
8
LSB
LSB
LSB
LSB
6
7 8
Dw1 Dw0
Dr2 Dr1 Dr0
Dw6 Dw7
Dr5 Dr6 Dr7
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