Epson S1C31D50 Technical Instructions page 203

Cycle No.
QSPI_nMOD.
QSPICLKn
LSBFST bit
QSDIOn1
QSDIOn0
0
QSDIOn1
QSDIOn0
QSDIOn1
QSDIOn0
1
QSDIOn1
QSDIOn0
Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
Cycle No.
QSPI_nMOD.
LSBFST bit
QSPICLKn
QSDIOn3
QSDIOn2
QSDIOn1
0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn1
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
1
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
Writing Dw[15:0] to the QSPI_nTXD register
Figure 15.4.3 Data Format Selection for Quad Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x2, QSPI_nMOD.CHLN[3:0] bits = 0x3, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
1
2
Dw15 Dw13 Dw11
Dw14 Dw12 Dw10
Dr15 Dr13 Dr11
Dr14 Dr12 Dr10
Dw0 Dw2 Dw4
Dw1 Dw3 Dw5
Dr0 Dr2 Dr4
Dr1 Dr3 Dr5
Writing Dw[15:0] to the QSPI_nTXD register
1
Dw15 Dw11
Dw14 Dw10
Dw13 Dw9
Dw12 Dw8
Dr15 Dr11
Dr14 Dr10
Dr13 Dr9
Dr12 Dr8
Dw0 Dw4
Dw1 Dw5
Dw2 Dw6
Dw3 Dw7
Dr0 Dr4
Dr1 Dr5
Dr2 Dr6
Dr3 Dr7
Seiko Epson Corporation
4
3 5 6
Dw9 Dw7 Dw5
Dw8 Dw6 Dw4
Dr9 Dr7 Dr5
Dr8 Dr6 Dr4
Dw6 Dw8 Dw10
Dw7 Dw9 Dw11
Dr6 Dr8 Dr10
Dr7 Dr9 Dr11
Loading Dr[15:0] to the QSPI_nRXD register
2 3
Dw7
Dw6
Dw5
Dw4
Dr7
Dr6
Dr5
Dr4
Dw8
Dw9
Dw10
Dw11
Dr8
Dr9
Dr10
Dr11
Loading Dr[15:0] to the QSPI_nRXD register
7 8
Dw3 Dw1
Dw2 Dw0
Dr3 Dr1
Dr2 Dr0
Dw12 Dw14
Dw13 Dw15
Dr12 Dr14
Dr13 Dr15
4
Dw3
Dw2
Dw1
Dw0
Dr3
Dr2
Dr1
Dr0
Dw12
Dw13
Dw14
Dw15
Dr12
Dr13
Dr14
Dr15
15-9