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REMC3 Data Bit Length Register
Register name
Bit
REMC3DBLEN
15–0
Bits 15–0
DBLEN[15:0]
These bits set the data length of the data signal (length of one cycle).
A data signal cycle begins with the 16-bit counter for data signal generation = 0x0000 and
ends when the counter exceeds the REMC3DBLEN.DBLEN[15:0] bit-setting value. (See
Figure 18.4.3.3.) Before this register can be rewritten, the REMC3DBCTL.MODEN bit must be
set to 1.
REMC3 Status and Interrupt Flag Register
Register name
Bit
REMC3INTF
15–11
10
9
8
7–2
1
0
Bits 15–11
Reserved
Bit 10
DBCNTRUN
This bit indicates whether the 16-bit counter for data signal generation is running or not.
(See Figure 18.4.4.1.)
1 (R): Running (Counting)
0 (R): Idle
Bit 9
DBLENBSY
This bit indicates whether the value written to the REMC3DBLEN.DBLEN[15:0] bits is
transferred to the REMC3DBLEN buffer or not. (See Figure 18.4.4.1.)
1 (R): Transfer to the REMC3DBLEN buffer has not completed.
0 (R): Transfer to the REMC3DBLEN buffer has completed.
While this bit is set to 1, writing to the REMC3DBLEN.DBLEN[15:0] bits is ineffective.
Bit 8
APLENBSY
This bit indicates whether the value written to the REMC3APLEN.APLEN[15:0] bits is
transferred to the REMC3APLEN buffer or not. (See Figure 18.4.4.1.)
1 (R): Transfer to the REMC3APLEN buffer has not completed.
0 (R): Transfer to the REMC3APLEN buffer has completed.
While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective.
Bits 7–2
Reserved
Bit 1
DBIF
Bit 0
APIF
These bits indicate the REMC3 interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt: REMC3INTF.DBIF
bit: Compare DB interruptREMC3INTF.APIF bit: Compare AP interrupt. These interrupt flags
are also cleared to 0 when 1 is written to the REMC3DBCTL.REMCRST bit.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
DBLEN[15:0]
0x0000
Bit name
Initial
–
0x00
DBCNTRUN
0
DBLENBSY
0
APLENBSY
0
–
0x00
DBIF
0
APIF
0
Seiko Epson Corporation
Reset
R/W
H0
R/W
Writing enabled when
REMC3DBCTL. MODEN bit = 1.
Reset
R/W
–
R
H0/S0
R
Cleared by writing 1 to the
REMC3DBCTL.REMCRST bit.
H0
R
Effective when the REMC3DBCTL.
BUFEN bit = 1.
H0
R
–
R
H0/S0
R/W
Cleared by writing 1 to this bit or
the REMC3DBCTL.REMCRST bit.
H0/S0
R/W
Remarks
Remarks
–
–
18-11
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