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Register access master mode
QSPI_nMOD register
CPOL bit
Slave mode
QSPI_nMOD register
CPOL bit
Memory mapped access mode
QSPI_nMOD register
CPOL bit
CPHA bit
1
0
QSPI_nINTF.MMABSY
Figure 15.6.1 QSPI_nINTF.BSY, QSPI_nINTF.MMABSY, and QSPI_nINTF.TENDIF Bit Set Timings
(when QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
QSPI_nINTF.BSY
QSPI_nINTF.TENDIF
#QSPISSn
QSPI_nINTF.BSY
CPHA bit
QSPICLKn
1
1
QSDIOn[3:0]
QSPICLKn
0
0
QSDIOn[3:0]
QSPI_nINTF.TENDIF
#QSPISSn
inactive period
(TCSH)
#QSPISSn
1
QSPICLKn
0
QSDIOn[3:0]
1 (W) → QSPI_nMMACFG2.MMAEN
Seiko Epson Corporation
1
2
Writing data to the QSPI_nTXD register
1
2
Writing data to the QSPI_nTXD register
Address cycle
Address cycle
(high-order 8/16 bits)
(low-order 16 bits)
3
4
3
4
Dummy cycle)
0 (W) → QSPI_nMMACFG2.MMAEN
15-31
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