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16.3.3. Baud Rate Generator
The I2C includes a baud rate generator to generate the serial clock SCL used in master mode. The I2C
set to slave mode does not use the baud rate generator, as it operates with the serial clock input from
the SCLn pin.
Setting data transfer rate (for master mode)
The transfer rate is determined by the I2C_nBR.BRT[6:0] bit settings. Use the following equations to
calculate the setting values for obtaining the desired transfer rate.
��
������_I2Cn
bps =
(������ + 3) × 2
Where
bps:
fCLK_I2Cn:
BRT:
* The equations above do not include SCL rising/falling time and delay time by clock stretching
(see Figure 16.3.3.1).
Note: The I
C bus transfer rate is limited to 100 kbit/s in Bold mode or 400 kbit/s in fast mode. Do
2
not set a transfer rate exceeding the limit.
Baud rate generator clock output and operations for supporting clock stretching
Figure 16.3.3.1 shows the clock generated by the baud rate generator and the clock waveform on the
I
C bus.
2
SCLn (external pin)
Clock stretching period by another I
Baud rate generator counting suspended period
Baud rate generator counting period
Figure 16.3.3.1 Baud Rate Generator Output Clock and SCLn Output Waveform
The baud rate generator output clock SCLO is compared with the SCLn pin status and the results
are returned to the baud rate generator. If a mismatch has occurred between SCLO and SCLn pin
levels, the baud rate generator suspends counting. This extends the clock to control data transfer
during the SCL signal rising/falling period and clock stretching period in which SCL is fixed at low by
a slave device.
16-4
������ =
Data transfer rate [bit/s]
I2C operating clock frequency [Hz]
I2C_nBR.BRT[6:0] bits setting value (1 to 127)
SCLO (internal
signal)
SCL rising/falling period
2
C device
Seiko Epson Corporation
��
������_I2Cn
− 3
(����. 16.1)
������ × 2
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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