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bit to the R/W bit value in the received address. If this value is 1, the I2C Ch.n sets the I2C_nINTF.TBEIF
bit to 1 and starts data sending operations.
Sending the first data byte
After the valid slave address has been received, the I2C Ch.n pulls down SCL to low and enters
standby state until data is written to the I2C_nTXD register. This puts the I
stretching state and the external master into standby state. When transmit data is written to the
I2C_nTXD register, the I2C Ch.n clears the I2C_nINTF.TBEIF bit and sends an ACK to the master.
The transmit data written in the I2C_ nTXD register is automatically transferred to the shift register
and the I2C_nINTF.TBEIF bit is set to 1. The data bits in the shift register are output in sequence to
the I
C bus.
2
Sending subsequent data
If the I2C_nINTF.TBEIF bit = 1, subsequent transmit data can be written during data transmission.
If the I2C_nINTF.TBEIF bit is still set to 1 when the data transmission from the shift register has
completed, the I2C Ch.n pulls down SCL to low (sets the I
transmit data is written to the I2C_nTXD register.
If the next transmit data already exists in the I2C_nTXD register or data has been written after
the above, the I2C Ch.n sends the subsequent eight-bit data when an ACK from the external master
is received. At the same time, the I2C_nINTF.BYTEENDIF bit is set to 1. If a NACK is received, the
I2C_nINTF.NACKIF bit is set to 1 without sending data.
STOP/repeated START condition detection
While the I2C_nCTL.MST bit = 0 (slave mode) and the I2C_nINTF.BSY = 1, the I2C Ch.n monitors the
I
C bus. When the I2C Ch.n detects a STOP condition, it terminates data sending operations. At
2
this time, the I2C_nINTF.BSY bit is cleared to 0 and the I2C_nINTF.STOPIF bit is set to 1. Also when the
I2C Ch.n detects a repeated START condition, it terminates data sending operations. In this case, the
I2C_nINTF.STARTIF bit is set to 1.
Clock stretching by I2C
2
S
Saddr/R
I
C bus
BSY = 1
TR = 1
STARTIF = 1
TBEIF = 1
Software bit operations
Operations by I2C (master mode)
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0),
Data n: 8-bit data
Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Data 1→ TXD[7:0] Data 2→ TXD[7:0] Data 3 → TXD[7:0]
A
Data 1
A
Data 2
TBEIF = 1
TBEIF = 1
BYTEENDIF = 1
Hardware bit operations
Operations by the external slave
Data transmission
Wait for an interrupt request
(I2C_nINTF.TBEIF = 1 or I2C_nINTF.NACKIF = 1)
I2C_nINTF.NACKIF = 1 ?
Yes
End
Figure 16.4.5.2 Slave Mode Data Transmission Flowchart
Seiko Epson Corporation
C bus into clock stretching state) until
2
Data N → TXD[7:0]
A
Data 3
A
P
TBEIF = 1
BSY = 0
NACKIF = 1
BYTEENDIF = 1
STOPIF = 1
BYTEENDIF = 1
Sr
Sr
No
Write data to the I2C_nTXD register
C bus into clock
2
Saddr/R
Data transmission
continued
BSY = 1
STARTIF = 1
TBEIF = 1
Saddr/W
Data reception
starts
TR = 0
BSY = 1
STARTIF = 1
16-13
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