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Data reception using DMA
For data reception, two DMA controller channels should be used to write dummy data to the
QSPI_nTXD register as a reception start trigger and to read the received data from the QSPI_nRXD
register.
By setting the QSPI_nTBEDMAEN.TBEDMAENx
bit to 1 (DMA transfer request enabled), a DMA
1
transfer request is sent to the DMA controller and dummy data is transferred from the specified
memory to the QSPI_ nTXD register via DMA Ch.x
when the QSPI_nINTF.TBEIF bit is set to 1 (transmit
1
buffer empty).
By setting the QSPI_nRBFDMAEN.RBFDMAENx
bit to 1 (DMA transfer request enabled), a DMA
2
transfer request is sent to the DMA controller and the received data is transferred from the
QSPI_nRXD register to the specified memory via DMA Ch.x
when the QSPI_nINTF.RBFIF bit is set to 1
2
(receive buffer full).
This automates the procedure from Step 3 to Step 9 described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on
DMA, refer to the "DMA Controller" chapter.
S1C31D50 TECHNICAL MANUAL
Seiko Epson Corporation
15-17
(Rev. 1.00)
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