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Figure 15.5.6.7 Data Reception Flowchart in Memory Mapped Access Mode
Data reception using DMA
In memory mapped access mode, DMA transfer from the external Flash memory to the internal
memory is al- lowed only for the 32-bit sequential read using the internal FIFO. A non-sequential
read and 8/16-bit reads can- not issue a DMA transfer request as they cannot use the FIFO.
By setting the QSPI_nFRLDMAEN.FRLDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and the external Flash memory data is transferred to
the specified internal memory via DMA Ch.x when the FIFO read level is incremented (FIFO data ready
flag is set). This function al- lows high-speed data block transfer as it does not need to execute read
commands and uses the data pre-fetched into the FIFO.
Note, however, that the first data read must be performed via software or a software triggered DMA.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on
DMA, refer to the "DMA Controller" chapter.
15-26
Data read
Assert the slave select signal output
from the #QSPISSn pin
(QSPI_nCTL.MSTSSO = 0)
Read the QSPI_nINTF.TBEIF bit
QSPI_nINTF.TBEIF = 1 ?
Y
e
Write an XIP read command to
the QSPI_nTXD register
Wait for an interrupt request
(QSPI_nINTF.TBEIF = 1)
Remap external Flash memory
(QSPI_nMADRH.RMADR[31:20])
Enable memory mapped access mode
(QSPI_nMMACF2.MMAEN = 1)
Read data from the memory mapped
access area
Read data remained?
N
o
Disable memory mapped access mode
(QSPI_nMMACF2.MMAEN = 0)
The slave select signal (#QSPISSn) is )
negated by the state machine.
End
Seiko Epson Corporation
N
o
Y
e
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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