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Bit 3
EXSEL
This bit selects the voltage to be detected when the SVD3CTL.VDSEL bit = 1.
1 (R/WP):
0 (R/WP):
Bits 2–1
SVDMD[1:0]
These bits select intermittent operation mode and its detection cycle.
Table 11.6.4 Intermittent Operation Mode Detection Cycle Selection
SVD3CTL.SVDMD[1:0] bits
For more information on intermittent and continuous operation modes, refer to "SVD3
Operations."
Bit 0
MODEN
This bit enables/disables for the SVD3 circuit to operate.
1 (R/WP):
0 (R/WP):
After this bit has been altered, wait until the value written is read out from this bit without
subsequent operations being performed.
Notes:
•
Writing 0 to the SVD3CTL.MODEN bit resets the SVD3 hardware. However, the register
values set and the interrupt flag are not cleared. The SVD3CTL.MODEN bit is actually set to
0 after this processing has finished. If 1 is written to the SVD3CTL.MODEN bit continuously
without waiting for the bit being read as 0 at this time, writing 0 may be ignored and a
mal- function may occur as the hardware restarts without resetting.
•
The SVD3 internal circuit is initialized if the SVD3CTL.SVDSC[1:0] bits,
SVD3CTL.SVDRE[3:0]bits, or SVD3CTL.SVDMD[1:0] bits are altered while SVD3 is in
operation after 1 is written to the SVD3CTL.MODEN bit.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
EXSVD1
EXSVD0
Operation mode (detection cycle)
0x3
Intermittent operation mode (CLK_SVD3/512)
0x2
Intermittent operation mode (CLK_SVD3/256)
0x1
Intermittent operation mode (CLK_SVD3/128)
0x0
Continuous operation mode
Enable (Start detection operations)
Disable (Stop detection operations)
Seiko Epson Corporation
11-9
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