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slave ad- dress bits and the R/W bit (= 0). If the received two high-order slave address bits are
matched with the I2C_ nOADR.OADR[9:8] bits, the I2C Ch.n returns an ACK. At this time, other
slaves may returns an ACK as the two high-order bits may be matched.
Then the master sends the eight low-order slave address bits as the second address. If this address
is matched with the I2C_nOADR.OADR[7:0] bits, the I2C Ch.n returns an ACK and starts data receiving
operations.
If the master issues a request to the slave to send data (data reception in the master), the master
generates a repeated START condition and sends the first address with the R/W bit set to 1. This
reception switches the I2C Ch.n to data sending mode.
At start of data reception
2
S
1stAddr/W
I
C bus
BSY = 1
At start of data transmission
2
S
1stAddr/W
I
C bus
BSY = 1
Figure 16.4.7.1 Example of Data Transfer Starting Operations in 10-bit Address Mode (Slave Mode)
16.4.8. Automatic Bus Clearing Operation
The I2C Ch.n set into master mode checks the SDA state immediately before generating a START
condition. If SDA is set to a low level at this time, the I2C Ch.n automatically executes bus clearing
operations that output up to ten clocks from the SCLn pin with SDA left free state.
When SDA goes high from low within nine clocks, the I2C Ch.n issues a START condition and starts
normal operations. If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is
regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit
to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1.
16-16
Clock stretching by I2C
STARTIF = 1
2ndAddr
A
A
Data 1
TR = 0
STARTIF = 1
Clock stretching by I2C
STARTIF = 1
Sr
1stAddr/R
A
2ndAddr
A
TR = 0
STARTIF = 1
Software bit operations
Operations by the external master
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, 1stAddr/W: 1st address + W(0), 1stAddr/R: 1st address + R(1),
2ndAddr: 2nd address, Data n: 8-bit data
Seiko Epson Corporation
RXD[7:0]→ Data 1
Data 2
A
A
RBFIF = 1
BYTEENDIF = 1
Data 1→TXD[7:0] Data 2→TXD[7:0]
A
A
Data 1
TBEIF = 1
TR = 1
STARTIF = 1
TBEIF = 1
Hardware bit operations
Operations by I2C (slave mode)
S1C31D50 TECHNICAL MANUAL
Data 2
TBEIF = 1
BYTEENDIF = 1
(Rev. 1.00)
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