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15.3. Clock Settings
15.3.1. QSPI Operating Clock
Operating clock in master mode
In master mode, the QSPI operating clock is supplied from the 16-bit timer. The following two
options are pro- vided for the clock configuration.
Use the 16-bit timer operating clock without dividing
By setting the QSPI_nMOD.NOCLKDIV bit to 1, the operating clock CLK_T16_m, which is configured
by selecting a clock source and a division ratio, for the 16-bit timer channel corresponding to the
QSPI channel is input to the QSPI as CLK_QSPIn. Since this clock is also used as the QSPI clock
QSPICLKn without changing, the CLK_QSPIn frequency becomes the baud rate.
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock
generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the
corresponding 16-bit timer channel are set (1 or 0).
When setting this mode, the timer function of the corresponding 16-bit timer channel may be used
for an- other purpose.
Use the 16-bit timer as a baud rate generator
By setting the QSPI_nMOD.NOCLKDIV bit to 0, the QSPI inputs the underflow signal generated by
the corresponding 16-bit timer channel and converts it to the QSPICLKn. The 16-bit timer must be
run with an appropriate reload data set. The QSPICLKn frequency (baud rate) and the 16-bit timer
reload data are calculated by the equations shown below.
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Where
f
: QSPICLKn frequency [Hz] (= baud rate [bps])
QSPICLK
f
: QSPI operating clock frequency [Hz]
CLK_QSPI
RLD: 16-bit timer reload data value
For controlling the 16-bit timer, refer to the "16-bit Timers" chapter.
Operating clock in slave mode
The QSPI set in slave mode operates with the clock supplied from the external SPI/QSPI master to
the QSPI- CLKn pin. The 16-bit timer channel (including the clock source selector and the divider)
corresponding to the QSPI channel is not used. Furthermore, the QSPI_nMOD.NOCLKDIV bit
setting becomes ineffective.
The QSPI keeps operating using the clock supplied from the external SPI/QSPI master even if all
the internal clocks halt during SLEEP mode, so the QSPI can receive data and can generate receive
buffer full interrupts.
15.3.2. Clock Supply During Debugging
In master mode, the operating clock supply during debugging should be controlled using the
T16_mCLK.DBRUN bit.
The CLK_T16_m supply to QSPI Ch.n is suspended when the CPU enters debug state if the
T16_mCLK.DBRUN bit = 0. After the CPU returns to normal operation, the CLK_T16_m supply resumes.
Although QSPI Ch.n stops operating when the CLK_T16_m supply is suspended, the output pins and
registers retain the status before the de- bug state was entered. If the T16_mCLK.DBRUN bit = 1, the
CLK_T16_m supply is not suspended and QSPI Ch.n will keep operating in a debug state.
The QSPI in slave mode operates with the external SPI/QSPI master clock input from the QSPICLKn pin
regard- less of whether the CPU is placed into debug state or normal operation state.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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15-7
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