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13.3. Clock Settings
13.3.1. UART3 Operating Clock
When using the UART3 Ch.n, the UART3 Ch.n operating clock CLK_UART3_n must be supplied to the
UART3 Ch.n from the clock generator. The CLK_UART3_n supply should be controlled as in the procedure
shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the
"Power Supply, Reset, and Clocks" chapter).
2. Set the following UART3_nCLK register bits:
UART3_nCLK.CLKSRC[1:0] bits
-
UART3_nCLK.CLKDIV[1:0] bits
-
The UART3 operating clock should be selected so that the baud rate generator will be configured
easily.
13.3.2. Clock Supply in SLEEP Mode
When using the UART3 during SLEEP mode, the UART3 operating clock CLK_UART3_n must be
configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UART3_n
clock source.
13.3.3. Clock Supply During Debugging
The CLK_UART3_n supply during debugging should be controlled using the UART3_nCLK.DBRUN bit.
The CLK_UART3_n supply to the UART3 Ch.n is suspended when the CPU enters debug state if the
UART3_ nCLK.DBRUN bit = 0. After the CPU returns to normal mode, the CLK_UART3_n supply resumes.
Although the UART3 Ch.n stops operating when the CLK_UART3_n supply is suspended, the output pin
and registers retain the status before the debug state was entered. If the UART3_nCLK.DBRUN bit = 1,
the CLK_UART3_n supply is not suspended and the UART3 Ch.n will keep operating in a debug state.
13.3.4. Baud Rate Generator
The UART3 includes a baud rate generator to generate the transfer (sampling) clock. The transfer rate is
determined by the UART3_nMOD.BRDIV, UART3_nBR.BRT[7:0], and UART3_nBR.FMD[3:0] bit settings. Use
the following equations to calculate the setting values for obtaining the desired transfer rate.
������_��������3
������ =
������+1
∗ ������
����������
Where
bps: Transfer rate [bit/s]
CLK_UART3:
BRDIV:
BRT:
FMD: UART3_nBR.FMD[3:0] setting value (0 to 15)
For the transfer rate range configurable in the UART3, refer to "UART Characteristics, Transfer baud
rates U
and U
" in the "Electrical Characteristics" chapter.
BRT1
BRT2
13-4
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
������ = ���������� × (
UART3 operating clock frequency [Hz]
Baud rate division ratio (1/16 or 1/4) * Selected by the UART3_nMOD.BRDIV bit
UART3_nBR.BRT[7:0] setting value (0 to 255)
Seiko Epson Corporation
������_��������3
− ������) − 1
������
S1C31D50 TECHNICAL MANUAL
(����. 13.1)
(Rev. 1.00)
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