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If no transmit data remains in the UART3_nTXD register after the stop bit has been output from the
USOUTn pin, the UART3_nINTF.TBSY bit is cleared to 0 and the UART3_nINTF.TENDIF bit is set to 1
(transmission completed).
USOUTn
UART3_nINTF.TBEIF
UART3_nINTF.TBSY
UART3_nINTF.TENDIF
Software operations
Read the UART3_nINTF.TBEIF bit
UART3_nINTF.TBEIF = 1 ?
Write transmit data to
the UART3_nTXD register
Transmit data remained?
Data transmission using DMA
By setting the UART3_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA
transfer request is sent to the DMA controller and transmit data is transferred from the specified
memory to the UART3_nTXD register via DMA Ch.x when the UART3_nINTF.TBEIF bit is set to 1
(transmit buffer empty). This automates the data sending procedure described above.
The transfer source/destination and control data must be set for the DMA controller and the
relevant DMA channel must be enabled to start a DMA transfer in advance so that transmit data
will be transferred to the UART3_nTXD register. For more information on DMA, refer to the "DMA
Controller" chapter.
Table 13.5.2.1 DMA Data Structure Configuration Example (for Data Transmission)
End pointer
Control data
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
st
D0 D1 D2 D3 D4 D5 D6 D7 p
Data (W) → UART3_nTXD
Data (W) → UART3_nTXD
Figure 13.5.2.1 Example of Data Sending Operations
Data transmission
Wait for an interrupt request
(UART3_nINTF.TBEIF = 1)
End
Figure 13.5.2.2 Data Transmission Flowchart
Item
Transfer source
Memory address in which the last transmit data is stored
Transfer destination
UART3_nTXD register address
dst_inc
0x3 (no increment)
dst_size
0x0 (byte)
src_inc
0x0 (+1)
src_size
0x0 (byte)
R_power
0x0 (arbitrated for every transfer)
n_minus_1
Number of transfer data
cycle_ctrl
0x1 (basic transfer)
Seiko Epson Corporation
sp
D0 D1
D7 p
sp
st
1 (W) → UART3_nINTF.TENDIF
(st: start bit, sp: stop bit, p: parity bit)
Setting example
st
sp
D0 D1
D7 p
Data (W) → UART3_nTXD
13-7
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