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UART3 Ch.n Interrupt Enable Register
Register name
Bit
UART3_nINTE
15–8
7
6
5
4
3
2
1
0
Bits 15–7
Reserved
Bit 6
TENDIE
Bit 5
FEIE
Bit 4
PEIE
Bit 3
OEIE
Bit 2
RB2FIE
Bit 1
RB1FIE
Bit 0
TBEIE
These bits enable UART3 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
UART3_nINTE.TENDIE bit: End-of-transmission interrupt
UART3_nINTE.FEIE bit:
UART3_nINTE.PEIE bit:
UART3_nINTE.OEIE bit:
UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt
UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt
UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register
Register name
Bit
UART3_nT BEDMAEN
15–0
Bits 15–0
TBEDMAEN[15:0]
These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective.
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
Register name
Bit
UART3_n RB1FDMAEN
15–0
Bits 15–0
RB1FDMAEN[15:0]
These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA
controller channel (Ch.0–Ch.15) when a receive buffer one byte full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the
unimplemented channels are ineffective
UART3 Ch.n Carrier Waveform Register
Register name
Bit
13-18
Bit name
Initial
–
0x00
–
0
TENDIE
0
FEIE
0
PEIE
0
OEIE
0
RB2FIE
0
RB1FIE
0
TBEIE
0
Framing error interrupt
Parity error interrupt
Overrun error interrupt
Bit name
Initial
TBEDMAEN[15:0]
0x0000
Bit name
Initial
RB1FDMAEN[15:0]
0x0000
Bit name
Initial
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Reset
R/W
H0
R/W
Reset
R/W
H0
R/W
Reset
R/W
Remarks
–
Remarks
–
Remarks
–
Remarks
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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