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REMC3 Interrupt Enable Register
Register name
Bit
REMC3INTE
15–8
7–2
1
0
Bits 15–2
Reserved
Bit 1
DBIE
Bit 0
APIE
These bits enable REMC3 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt: REMC3INTE.DBIE
bit: Compare DB interrupt
REMC3INTE.APIE bit: Compare AP interrupt
REMC3 Carrier Waveform Register
Register name
Bit
REMC3CARR
15–8
7–0
Bits 15–8
CRDTY[7:0]
These bits set the high level period of the carrier signal.
The carrier signal is set to high level from the 8-bit counter for carrier generation = 0x00
and it is in- verted to low level when the counter exceeds the REMC3CARR.CRDTY[7:0]
bit-setting value. The carrier signal duty ratio is determined by this setting and the
REMC3CARR.CRPER[7:0] bit-setting. (See Figure 18.4.3.2.)
Bits 7–0
CRPER[7:0]
These bits set the carrier signal cycle.
A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends
when the counter exceeds the REMC3CARR.CRPER[7:0] bit-setting value. (See Figure
18.4.3.2.)
REMC3 Carrier Modulation Control Register
Register name
Bit
REMC3CCTL
15–9
8
7–1
0
Bits 15–9
Reserved
Bit 8
OUTINVEN
This bit inverts the REMO output polarity.
1 (R/W): Inverted
0 (R/W): Non-inverted
For more information, see Figure 18.4.3.1.
Bits 7–1
Reserved
Bit 0
CARREN
This bit enables carrier modulation.
1 (R/W): Enable carrier modulation
0 (R/W): Disable carrier modulation (output data signal only)
Note:
When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0.
18-12
Bit name
Initial
–
0x00
–
0x00
DBIE
0
APIE
0
Bit name
Initial
CRDTY[7:0]
0x00
CRPER[7:0]
0x00
Bit name
Initial
–
0x00
OUTINVEN
0
–
0x00
CARREN
0
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/W
H0
R/W
Reset
R/W
H0
R/W
H0
R/W
Reset
R/W
–
R
H0
R/W
–
R
H0
R/W
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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