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15.7. DMA Transfer Requests
The QSPI has a function to generate DMA transfer requests from the causes shown in Table 15.7.1.
Cause to
DMA transfer request
request
DMA transfer
Receive buffer
Receive buffer full flag
full
(QSPI_nINTF.RBFIF)
Transmit buffer
Transmit buffer empty
empty
flag (QSPI_nINTF.TBEIF)
Memory
Memory mapped
mapped access
access FIFO data ready
FIFO data ready
flag (internal signal)
The QSPI provides DMA transfer request enable bits corresponding to each DMA transfer request
flag shown above for the number of DMA channels. A DMA transfer request is sent to the pertinent
channel of the DMA controller only when the DMA transfer request flag, of which DMA transfer has
been enabled by the DMA transfer request enable bit, is set. The receive buffer full and transmit buffer
empty DMA transfer request flags also serve as interrupt flags, therefore, both the DMA transfer request
and the interrupt cannot be enabled at the same time. After a DMA transfer has completed, disable the
DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on
the DMA control, refer to the "DMA Controller" chapter.
15-32
Table 15.7.1 DMA Transfer Request Causes of QSPI
flag
When data of the specified bit length is
received and the received data is transferred
from the shift register to the received data
buffer
When transmit data written to the transmit
data buffer is transferred to the shift register
When a 32-bit data is prefetched into the
FIFO in memory mapped access mode
Seiko Epson Corporation
Set condition
S1C31D50 TECHNICAL MANUAL
Clear condition
Reading of the
QSPI_
nRXD register
Writing to the
QSPI_
nTXD register
When the FIFO
read level is
cleared to 0
(Rev. 1.00)
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