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RTCA Stopwatch Control Register
Register name
Bit
RTCASWCTL
15–12
11–8
7–5
4
3–1
0
Bits 15–12
BCD10[3:0]
Bits 11–8
BCD100[3:0]
The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a
BCD code from the RTCASWCTL.BCD10[3:0] bits and the RTCASWCTL.BCD100[3:0] bits,
respectively.
Note:
The counter value may not be read correctly while the stopwatch counter is running. The
RT- CASWCTL.BCD10[3:0]/BCD100[3:0] bits must be read twice and assume the counter
value was read successfully if the two read results are the same.
Bits 7–5
Reserved
Bit 4
SWRST
This bit resets the stopwatch counter to 0x00.
1 (W): Reset
0 (W): Ineffective
0 (R): Always 0 when being read
When the stopwatch counter in running status is reset, it continues counting from count
0x00. The stopwatch counter retains 0x00 if it is reset in idle status.
Bits 3–1
Reserved
Bit 0
SWRUN
This bit starts/stops the stopwatch counter.
1 (R/W): Running/start control
0 (R/W): Idle/stop control
When the stopwatch counter stops counting by writing 0 to this bit, the counter retains the
value when it stopped. Writing 1 to this bit again resumes counting from the value
retained.
Note:
The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the RT-
CASWCTL.SWRUN bit. Therefore, the counter value may be incremented (+1) from the
value at writing 0.
10-12
Bit name
Initial
BCD10[3:0]
0x0
BCD100[3:0]
0x0
–
0x0
SWRST
0
–
0x0
SWRUN
0
Seiko Epson Corporation
Reset
R/W
H0
R
H0
R
–
R
H0
W
–
R
H0
R/W
Remarks
–
Read as 0.
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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