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15. Quad Synchronous Serial Interface
(QSPI)
15.1. Overview
The QSPI is a quad synchronous serial interface. The features of the QSPI are listed below.
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Supports both master and slave modes.
•
Supports single, dual, and quad transfer modes.
•
Data length: 2 to 16 clocks programmable.
•
Data line drive length: 1 to 16 clocks programmable (for output direction only).
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Either MSB first or LSB first can be selected for the data format.
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Clock phase and polarity are configurable.
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Supports full-duplex communications.
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Includes separated transmit data buffer and receive data buffer registers.
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Can generate receive buffer full, transmit buffer empty, end of transmission, and overrun
interrupts.
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Master mode allows use of a 16-bit timer to set baud rate.
•
Slave mode is capable of being operated with the external input clock QSPICLKn only.
•
Slave mode is capable of being operated in SLEEP mode allowing wake-up by a QSPI interrupt.
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Input pins can be pulled up/down with an internal resistor.
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Low CPU overhead memory mapped access mode that can access the external Flash memory with
XIP (eXecute- In-Place) mode in the same manner as the embedded system memory.
Memory mapped access size: 8, 16, and 32-bit access.
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1M-byte external Flash memory mapping area starting at 0x0008_0000 that allows
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programmable re-mapping.
Configurable 3 or 4-byte address cycle length.
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Single, dual, or quad transfer mode is configurable for each address, mode byte/dummy, and
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data cycle.
Programmable mode bytes for both XIP mode activation and termination.
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Configurable mode byte/dummy output cycle length.
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•
Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a
memory mapped access (32-bit read) occurs.
Figure 15.1.1 shows the QSPI configuration.
Number of channels
Internal clock input
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 15.1.1 QSPI Channel Configuration of S1C31D50
Item
Seiko Epson Corporation
S1C31D50
1 channels (Ch.0)
Ch.0 ← 16-bit timer Ch.2
15-1
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