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9.3.2. Operations in HALT and SLEEP Modes
During HALT mode
WDT2 operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for
more than the NMI/reset generation cycle and the CPU executes the interrupt handler. To disable
WDT2 in HALT mode, stop WDT2 by writing 0xa to the WDT2CTL.WDTRUN[3:0] bits before executing
the halt instruction. Reset WDT2 before re- suming operations after HALT mode is cleared.
During SLEEP mode
WDT2 operates in SLEEP mode if the selected clock source is running. SLEEP mode is cleared by an
NMI or reset if it continues for more than the NMI/reset generation cycle and the CPU executes the
interrupt handler. Therefore, stop WDT2 by setting the WDT2CTL.WDTRUN[3:0] bits before executing
the slp instruction.
If the clock source stops in SLEEP mode, WDT2 stops. To prevent generation of an unnecessary NMI
or reset after clearing SLEEP mode, reset WDT2 before executing the slp instruction. WDT2 should
also be stopped as required using the WDT2CTL.WDTRUN[3:0] bits.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
9-3
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