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14.5. Operations
14.5.1. Initialization
SPIA Ch.n should be initialized with the procedure shown below.
1. <Master mode only> Generate a clock by controlling the 16-bit timer and supply it to SPIA Ch.n.
2. Configure the following SPIA_nMOD register bits:
SPIA_nMOD.PUEN bit
-
SPIA_nMOD.NOCLKDIV bit
-
SPIA_nMOD.LSBFST bit
-
SPIA_nMOD.CPHA bit
-
SPIA_nMOD.CPOL bit
-
SPIA_nMOD.MST bit
-
3. Assign the SPIA Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
4. Set the following SPIA_nCTL register bits:
Set the SPIA_nCTL.SFTRST bit to 1. (Execute software reset)
-
Set the SPIA_nCTL.MODEN bit to 1. (Enable SPIA Ch.n operations)
-
5. Set the following bits when using the interrupt:
Write 1 to the interrupt flags in the SPIA_nINTF register.
-
Set the interrupt enable bits in the SPIA_nINTE register to 1. *
-
*The initial value of the SPIA_nINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after
the SPIA_nINTE.TBEIE bit is set to 1.
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer:
Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN
-
registers. (Enable DMA transfer requests)
14.5.2. Data Transmission in Master Mode
A data sending procedure and operations in master mode are shown below. Figures 14.5.2.1 and
14.5.2.2 show a timing chart and a flowchart, respectively.
Data sending procedure
1. Assert the slave select signal by controlling the general-purpose output port (if necessary).
2. Check to see if the SPIA_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
3. Write transmit data to the SPIA_nTXD register.
4. Wait for an SPIA interrupt when using the interrupt.
5. Repeat Steps 2 to 4 (or 2 and 3) until the end of transmit data.
6. Negate the slave select signal by controlling the general-purpose output port (if necessary).
Data sending operations
SPIA Ch.n starts data sending operations when transmit data is written to the SPIA_nTXD register.
The transmit data in the SPIA_nTXD register is automatically transferred to the shift register and
the SPIA_ nINTF.TBEIF bit is set to 1. If the SPIA_nINTE.TBEIE bit = 1 (transmit buffer empty
interrupt enabled), a transmit buffer empty interrupt occurs at the same time.
The SPICLKn pin outputs clocks of the number of the bits specified by the SPIA_nMOD.CHLN[3:0]
bits and the transmit data bits are output in sequence from the SDOn pin in sync with these clocks.
Even if the clock is being output from the SPICLKn pin, the next transmit data can be written to
the SPIA_
nTXD register after making sure the SPIA_nINTF.TBEIF bit is set to 1.
If transmit data has not been written to the SPIA_nTXD register after the last clock is output from
the SPI- CLKn pin, the clock output halts and the SPIA_nINTF.TENDIF bit is set to 1. At the same time
SPIA issues an end-of-transmission interrupt request if the SPIA_nINTE.TENDIE bit = 1.
14-6
(Enable input pin pull-up/down)
(Select master mode operating clock)
(
Select MSB first/LSB first)
(Select clock phase)
(Select clock polarity)
(Select master/slave mode)
Seiko Epson Corporation
(Clear interrupt flags)
(Enable interrupts)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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