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DMAC Primary-Alternate Set Register
Register name
Bit
DMACPASET
31–0
Bits 31–0
PASET[31:0]
These bits enable the alternate data structures.
1 (W): Enable alternate data structure
0 (W): Ineffective
1 (R): The alternate data structure has been enabled.
0 (R): The primary data structure has been enabled.
Each bit corresponds to a DMAC channel. The high-order bits for the
unimplemented channels are ineffective.
DMAC Primary-Alternate Clear Register
Register name
Bit
DMACPACLR
31–0
Bits 31–0
PACLR[31:0]
These bits disable the alternate data structures.
1 (W): Disable alternate data structure (The DMACPASET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Priority Set Register
Register name
Bit
DMACPRSET
31–0
Bits 31–0
PRSET[31:0]
These bits increase the priority of each channel.
1 (W): Increase priority
0 (W): Ineffective
1 (R): Priority = High
0 (R): Priority = Normal
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Priority Clear Register
Register name
Bit
DMACPRCLR
31–0
Bits 31–0
PRCLR[31:0]
These bits decrease the priority of each channel.
1(W): Decrease priority (The DMACPRSET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
6-16
Bit name
Initial
PASET[31:0]
0x0000
0000
Bit name
Initial
PACLR[31:0]
–
Bit name
Initial
PRSET[31:0]
0x0000
0000
Bit name
Initial
PRCLR[31:0]
–
Seiko Epson Corporation
Reset
R/W
H0
R/W
Reset
R/W
–
W
Reset
R/W
H0
R/W
Reset
R/W
–
W
Remarks
–
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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