Epson S1C31D50 Technical Instructions page 215

QSPI_nMOD register
CPOL bit CPHA bit
1 1
0 0
Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
HCLK
HSEL
HADDR
n
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
2
QSPICLKn
QSDIOn[3:0]
Seiko Epson Corporation
n+4 n+8
2
2
n n+4
1
0
Data cycle
(for n+8)
n+8
1 0
Data cycle
(prefetching))
15-21